1. Field of the Invention
The invention relates to silicon integrated circuit processing and, more particularly, to a process for reducing cell to cell shorts in integrated circuits.
2. Description of the Related Art
A continued increase in device packing density of integrated circuits requires a continued reduction in cell sizes without compromising device integrity. The trend toward smaller cell sizes in a densely packed circuit has invariably increased the occurrence of defects, such as cell to cell shorts. Cell to cell shorts occur when current from one cell strays to adjacent cells via a path along the surface of the isolation material between the cells, causing electrical bridging between two adjacent devices. This can result in damage to the adjacent cells or can hinder proper performance of the circuit.
The occurrence of cell to cell shorts is substantially more frequent in a densely packed circuit because the shortened distance between cells makes it much easier for the current to reach adjacent devices. In fact, this problem of cell to cell shorts is especially prevalent between capacitor cells in DRAM applications, particularly in DRAM circuits where the cells are positioned closer together to achieve greater scales of integration.
In particular, a DRAM cell typically consists of an access device, such as a transistor formed in a semiconductor substrate connected to a charge storage capacitor that is formed on top of the substrate adjacent the transistor such that the transistor can activate the capacitor. One typical capacitor configuration in a DRAM cell is similar in form to that of a container. To form the container shaped capacitor, two layers of conductive material, separated by a layer of dielectric, is deposited into an etched opening on one or more pre-deposited layers of isolation material, where the bottom of the openings exposes the access devices. The etched openings in the isolation material define a plurality of cell containers because they resemble, in shape and function, a container into which individual devices such as capacitors can be formed and isolated from each other.
The individual cell containers are typically arranged in an array on the substrate and are electrically separated from each other by the isolation material formed in between. Increased device packing density in DRAM cells requires cell containers to be placed closer together, with much less space separating individual devices, resulting in an increase of cell to cell shorts between adjacent devices, such as capacitors.
In addition to the shrinking distance between adjacent devices, cell to cell shorts can also occur as a consequence of a particular texturizing process used in manufacturing some DRAM cells. As it is understood in the art, each charge stored in a DRAM memory cell signifies a memory bit and increasing the amount of stored charge will enhance the memory function of the cell. Since the amount of charge a cell is able to store, i.e. the capacitance, varies directly with the surface area of the capacitor electrodes, any enhancement in cell capacitance typically involves increasing the electrode surface area.
As the packing density of cell capacitors has increased, the area allotted for each cell has diminished, yet the required cell capacitance has remained the same or even increased in some cases. It is therefore desirable to manufacture a capacitor with increased electrode surface area but without consuming additional cell space so that the cell capacitance can be increased despite of shrinking cell areas. One method of maintaining or increasing the electrode surface area in the face of shrinking cell space is to texturize the electrode surface.
One typical texturizing process comprises performing a seeding step in which nucleation sites are generated on the container shaped electrodes. Typically this is accomplished by depositing a material such as silicon on the substrate surface containing the electrodes, followed by an annealing process resulting in a textured electrode surface having a hemispherically grained morphology (HSG) as described, for example, in U.S. Pat. No. 5,830,793. The HSG textured electrodes have an enhanced surface area yet do not consume additional cell space. The HSG seeding process, however, frequently leaves conductive deposits such as polysilicon on the dielectric material between the electrodes, which in turn could potentially create a cell to cell short between neighboring electrodes in a densely packed circuit. Electrical shorts will occur more frequently as the polysilicon inadvertently deposited on the isolation material further facilitates the flow of current along an already shortened path between adjacent electrodes.
To reduce the occurrence of such cell to cell shorts, a post-etch process is typically used to remove the excess poly deposits on the dielectric surface. The post-etch process, however, not only requires additional resources and time during fabrication, but can also damage the textured electrodes by indiscriminately removing the polysilicon deposited on the electrodes along with the polysilicon found on the isolation material between the cells. Thus it is desirable to have a method of reducing the cell to cell shorts and, in particular, a method that does not compromise the textured electrode surfaces of DRAM cells.
Hence, from the foregoing, it will be appreciated that there is a need for a process for reducing shorts between adjacent cells on a semiconductor substrate that does not require additional processing steps. To this end, there is a particular need for a process of reducing shorts between adjacent capacitors on a DRAM memory circuit, and specifically texturized capacitors, that does not require additional potentially damaging etch steps.
The aforementioned needs are satisfied by the integrated circuit of the present invention. In one aspect, the present invention comprises a semiconductor substrate having a first surface with at least one isolation layer formed on the first surface of the substrate. The at least one isolation layer defines a plurality of cell containers that are located within the at least one isolation layer so that adjacent cell containers are at least a first distance apart. A plurality of cells are formed in the cell containers and the at least one isolation layer is contoured so that a surface path interconnecting adjacent cells of the plurality of cells is greater than the first distance. An increase in the surface path reduces the amount of leakage current travelling between adjacent cells.
In one embodiment, the cell containers are configured so as to have a first region of a first cross-sectional area located proximal the first surface of the substrate and a second region of a second cross-sectional area located distal from the first surface of the substrate. The second cross-sectional area is larger than the first cross-sectional area. In this embodiment, the at least one isolation layer is contoured so that a first surface of the at least one isolation layer located between adjacent cell containers is located in a plane that intersects the first region of the cell container. In this way, the surface path linking adjacent cells formed in adjacent cell containers includes one or more path lengths that extend inward towards the first surface and, thus, the surface path length for leakage currents between adjacent cells is increased.
In one particular embodiment, the cell containers can include capacitor cells. Moreover, in one embodiment, the isolation region can be contoured or formed so that the surface path between adjacent cells includes two paths lengths which are substantially perpendicular to the plane of the first surface of the semiconductor surface.
In another aspect of the present invention, a method of forming electrical cells on a semiconductor substrate is provided. The method comprises positioning at least one isolation layer on a first surface of the substrate, forming a plurality of cell containers in the at least one isolation layer so that the plurality of cell containers are at least a first distance apart, positioning cells in the plurality of cell containers so that the outer boundary of the cells conform to the inner surface of the cell containers, and contouring the at least one isolation layer between the plurality of cell containers so that a surface path for current to travel between the adjacent cells is greater than the first distance between the cell containers.
In one embodiment the cell containers are formed so that the cell containers include a first region and a second region located proximal the first surface of the substrate so that the first region has a first cross-sectional area and a second region located distal from the substrate has a second cross-sectional area greater than the first cross-sectional area. In this embodiment, the isolation layer is formed or contoured so that a first surface of the isolation layer between adjacent cells is located so as to be closer to the first surface of the substrate than a transition point between the first and second regions of the cell containers.
From the foregoing, it will be appreciated that the aspects of the present invention provide both a circuit and a method of fabricating electrical cells where the surface path between adjacent cells is increased. The increase in the surface path reduces leakage currents. As the surface path is increased due to contouring of the isolation layer, e.g., by etching or removing portions of the isolation layer, the decrease in the surface path can be achieved while reducing the risk of damage to the electrical cells. These and other objects and advantages of the present invention will become more apparent from the following description taken in conjunction with the following drawings.